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Forum Post: RE: RX210 RSK clock generation issue

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Thanks for your quick response Paul. I did some tests as you suggested and it definitely makes a difference. Optimization is affecting toggle time and with level 2 setting it reduces from 1ms to 400us which is 12.5MHz system tick. This is still off from what the setting expects (50MHz sys clock), but is this the wright way to calculate it as time is lost in instructions anyway. Main code not optimized: do { P17data = !P17data; // Toggle P17 PORT1.PODR.BIT.B7 = P17data; MOV.L       20H[R0],R14 MOV.L       R14,R4 MOV.L       #08C001H,R5 BTST        #0,R4 BMC         #7,20H[R5] for  (Delay = 5E3; Delay 0; Delay--)    // Delay of 1ms 50MHz ICLK; 100ms(400E3); 20us(80) //5E4 for MOV.L       #1388H,R14 MOV.L       R14,24H[R0] MOV.L       24H[R0],R14 CMP         #0H,R14 BLE.B       0FFFF1323H { nop(); NOP         MOV.L       24H[R0],R14 SUB         #1H,R14 MOV.L       R14,24H[R0] MOV.L       24H[R0],R14 CMP         #0H,R14 BGT.B       0FFFF1313H MOV.L       #0H,R14 CMP         #1H,R14 BNE.B       0FFFF12E8H ADD         #34H,R0,R0 RTS         } } while(1); } Level 2 Optimization: do { P17data = !P17data; // Toggle P17 CMP         #0H,R4 SCEQ.L      R5 MOV.L       R5,R4 BTST        #0,R5 BMC         #7,20H[R3] MOV.L       #1388H,R5 PORT1.PODR.BIT.B7 = P17data; for  (Delay = 5E3; Delay 0; Delay--)    // Delay of 1ms 50MHz ICLK; 100ms(400E3); 20us(80) //5E4 for SUB         #1H,R5 BNE.B       0FFFF0A3DH BRA.B       0FFFF0A2CH { nop(); NOP         SUB         #1H,R5 BNE.B       0FFFF0A3DH BRA.B       0FFFF0A2CH } while(1); } Adding a single nop() constitudes to 100us loop delay, which is overall surprisingly high to me. Would you know for any other way to check system clock speed? Thanks

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