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Forum Post: RX210 RSK clock generation issue

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Hi everyone, I am currently developing software that aims to run on 50MHz system clock. Peripheral Drive Generator (PDG2) file is linked to my project but this is only to help with board configuration, as I do not use any of the functions generated. My clock, port and module initiation is done through registers. Clock initiation sequence: SYSTEM.PRCR.WORD = 0xA507;        // Protect Register OFF SYSTEM.OPCCR.BYTE = 0x00;           // High-speed Mode MSTP(MTU0) = 0;                                  // MTU0 module stop state is cancelled MSTP(S12AD) = 0;                                // AD Converter module stop state is cancelled MSTP(DA) = 0;                                      // DAC module stop state is cancelled SYSTEM.PRCR.WORD = 0xA500;      // Protect Register ON SYSTEM.PRCR.WORD = 0xA503; SYSTEM.SYSCR0.WORD = 0x5A03;  // External bus enable bit SYSTEM.VRCR = 0x00;                       // Voltage Regulator Control Register /* PLL Clock Setting */ SYSTEM.SOSCCR.BYTE = 0x01;          // Sub-clock oscillator OFF SYSTEM.HOCOPCR.BYTE = 0x01;       // HOCO PSU OFF SYSTEM.HOCOCR.BYTE = 0x01;         // HOCO OFF SYSTEM.MOSCCR.BYTE = 0x01;         // EXTAL OFF SYSTEM.MOSCWTCR.BYTE = 0x0D;   // Main Clock Oscillator Wait Control Register SYSTEM.MOSCCR.BYTE = 0x00;         // EXTAL ON SYSTEM.PLLWTCR.BYTE = 0x0D;       // PLL Wait Control Register SYSTEM.PLLCR2.BYTE = 0x01;           // PLL OFF SYSTEM.PLLCR.WORD = 0x0901;       // 20 MHz / 2; 10 MHz * 10 = 100 MHz SYSTEM.PLLCR2.BYTE = 0x00;           // PLL ON // internal LOCO circuit - 125kHz for(i = 0; i 2500; i++) {}                        // 20 ms SYSTEM.SCKCR.LONG = (unsigned long)0x21031211;  // ICK= 50MHz ;Psop =0enabled;0000; PCLKB=25MHz;0000; PCLKD=50MHz SYSTEM.SCKCR3.WORD = 0x0400; // LOCO to PLL SYSTEM.PRCR.WORD = 0xA500; The issue is, when I run a simple LED toggle (Port17) to measure loop time, I get 1ms delay at 5000 counts. This calculates 5MHz system clock whereas the SCKCR indicates setting for 50MHz. In parallel with this measurement I read correct setting on external bus clock (Port53) BCLK which is set for 12.5MHz. Is it possible to have module clocks wrongly initiated above as I do not have major delays in program loop? Any help is appreciated.

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