Hi, In the HW manual for RX parts under "I/O Registers" there is mentioned in "Notes on writing to I/O registers" that it takes some cycles to complete IEN = 0 (pipe lining). Polling the IEN bit is advised to ensure that it is cleared before any critical subsequent instructions are executed. I had a look at how the portENTER_CRITICAL() in FreeRTOS is implemented. It basically sets the IPL in the PSW register to a priority level such that all interrupts associated with the FreeRTOS are turned off. I assume that this IPL instruction also needs some cycles to complete, so I would suspect that FreeRTOS should include a polling mechanism to ensure that the IPL has been set to its value before continuing. I am posting this here so that the community can either confirm that is is a potential issue, or to explain that this poses no problem. Any help is welcome! HC
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