Hello, the RL78 doesn't support moving the vector table to RAM by hardware. Alternatively you can fill the HW vector table with branch instructions to a virtual vector table, which has to be located within the first 64KB Flash (= near area). The virtual vector table uses 24bit branch instructions (= far branch) to reach the ISR functions located in RAM. Here is an example for the IAR assembler: COMMON INTVEC:CODE:ROOT(1) #define BASE_VIRTUAL_IRQ 0x8C00 DS 2 ; Reset vector DS 2 ; reserved DC16 BASE_VIRTUAL_IRQ + 0x0006 ; 0x04 DC16 BASE_VIRTUAL_IRQ + 0x0009 ; 0x06 DC16 BASE_VIRTUAL_IRQ + 0x000C ; 0x08 DC16 BASE_VIRTUAL_IRQ + 0x000F ; 0x0A DC16 BASE_VIRTUAL_IRQ + 0x0012 ; 0x0C DC16 BASE_VIRTUAL_IRQ + 0x0015 ; 0x0E ... DC16 BASE_VIRTUAL_IRQ + 0x00B7 ; 0x7A DC16 BASE_VIRTUAL_IRQ + 0x00BA ; 0x7C DC16 BASE_VIRTUAL_IRQ + 0x00BD ; 0x7E END and here is virtual IRQ table: EXTERN sp_init EXTERN INTWDTI_isr EXTERN INTLVI_isr EXTERN INTP0_isr EXTERN INTP1_isr EXTERN INTP2_isr EXTERN INTP3_isr ... EXTERN INTP11_isr EXTERN INTMD_isr EXTERN INTFL_isr RSEG VINTVEC:CODE:ROOT(1) br sp_init ds 3 ; (0x02) br INTWDTI_isr ; (0x04) br INTLVI_isr ; (0x06) br INTP0_isr ; (0x08) br INTP1_isr ; (0x0A) br INTP2_isr ; (0x0C) ... ds 3 ; (0x58) ds 3 ; (0x5A) ds 3 ; (0x5C) br INTMD_isr ; (0x5E) ds 3 ; (0x60) br INTFL_isr ; (0x62) ds 3 ; (0x64) ds 3 ; (0x66) ds 3 ; (0x68) ds 3 ; (0x6A) ds 3 ; (0x6C) ds 3 ; (0x6E) ds 3 ; (0x70) ds 3 ; (0x72) ds 3 ; (0x74) ds 3 ; (0x76) ds 3 ; (0x78) ds 3 ; (0x7A) ds 3 ; (0x7C) ds 3 ; (0x7E) END
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