Hi Ellen. Your errors indicate that the CAN bus is offline. This is most likely due to having improper bit rate settings or a bad hardware connection. Setting the bit rate registers is arguably the most difficult part of getting CAN to work. Here's what you need to do: 1) Set the bit rate clock source in r_rscan_rx_config.h. It can use either Peripheral Clock B (PCLKB) at half speed, or the EXTAL pin input. The default is to use EXTAL which is 8MHz on the RSKRX231. /* * Setting for CAN clock source. * 0 = PCLKB/2 * 1 = CANMCLK = EXTAL pin // RSKRX231 */ #define CAN_CFG_CLOCK_SOURCE (1) 2) Note that divisors from 1 to 1024 can be applied to this clock source. This slower clock speed is used for sampling bits on the network. One clock cycle of this slower clock speed is called a Time Quantum (Tq). 3) Now here's the hard part. Ideally, a bit is sampled around 80% into its transmission. This allows for edge transition detection and for physical delay in processing (2 times delay on bus + input comparator delay + output driver delay). These segments are illustrated in Figure 36.17 in the Hardware Manual. The following rules must be applied when calculating segment duration: SS = 1 Tq TSEG1 = 4 to 16 Tq TSEG2 = 2 to 8 Tq SJW = 1 to 4 Tq TSEG1 TSEG2 SJW SS + TSEG1 + TSEG2 = 8 to 25 Tq To calculate the number of time quanta needed for a baud rate, first determine the clock divisor via the following formula: CAN clock / bitrate = total Tq If the number of time quanta (Tq) is greater than 25, apply a divisor until the number is between 8 and 25. For example, if the source clock speed is 8 Mhz and the desired bit rate is 250Kbps, 8000000 / 250000 = 32. This is greater than 25 so a divisor must be used. If we apply a divisor of 2 we get 16 Tq (8MHz/2 /250Kbps). Applying a divisor of 4 we get 8 Tq. Both are in the range of 8 to 25. Next is assigning Tq to each segment. 80% of 8 total Tq is 6.4. 80% of 16 total Tq is 12.8. Therefore, rounding to the nearest integer without exceeding 80%, SS + TSEG1 should contain 6 or 12 Tq depending upon the divisor, and the remaining Tq are assigned to TSEG2. clock source divisor desired bit rate Total Tq SS TSEG1 TSEG2 (SJW) Actual sample point 8 MHz 4 250KHz 8 1 5 2 1 6 / 8 = 75% 8 MHz 2 250KHz 16 1 11 4 1 12 / 16 = 75% 1 10 5 1 11 / 16 = 68.75% Both divisors provide a sampling point of 75% into the bit, so either one may be used. Often, the smaller divisor is chosen so there is a larger number of Tq to work with. Minor adjustments to Tq segment assignment may be needed to account for variations of the devices on the network. For example, when using a divisor of 2 in this example, an alternate assignment of 1, 10, 5, 1 to the segments (sampling point at 68.75% into bit time) may actually perform better. This can only be determined with testing on the actual network. The Tq values chosen are loaded into a st_can_bitrate structure and passed into the R_CAN_InitChan() function. typedef struct st_can_bitrate { uint16_t prescaler; // 1-1024 (divisor) uint8_t tseg1; // 4-16 uint8_t tseg2; // 2-8 uint8_t sjw; // 1-4 } can_bitrate_t; Hope this helps!
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