1) Download an_r01an2162ej0200_rza1h_other.zip packet from Renesas web site 2) I'm using e2studio 3.1.1.07 3) Copy 'common' folder in '../workspace/RZA1h_RGA_Sample/RGA_Sample/kpitgcc' folder. You can find this 'common' folder inside the armcc project. Then import kpitgcc in e2studio as an existing DS5 project. 4) You should change linker script file name into kpitgcc.ld 5) You should also add libkpitgcc.a lib file inside the project Debug folder. 6) I'm using Vekatech VK-RZ/A1H-2.0 board for testing purposes, along with tft-lcd display VK-LCD50RTA companion board (http://www.vekatech.com/products2.php?id=2) I strongly reccommend to download and study schematic pdf files in order to understand what hardware pins are really involved in the tft-lcd handling. (For example pin P8_15 does turn the display on, and in pwm fashion it makes possible to dim tft light background) 7) I had to modify initialization of ports and pins and tft-lcd timing generation according to the hardware I have got. And it is important to check that previous hardware settings (already in the Renesas starting project) are not incompatible with my new hardware configuration. One of the most important file to modify is: lcd_analog_rgb_ch0.c --- start file /******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /**************************************************************************//** * @file lcd_analog_rgb_ch0.c * @version 1.00 * $Rev: 199 $ * $Date:: 2014-05-23 16:33:52 +0900#$ * @brief LCD panel for vdc5 channel 0 function ******************************************************************************/ /****************************************************************************** Includes System Includes , "Project Includes" ******************************************************************************/ #include string.h #include "r_typedefs.h" #include "r_vdc5.h" #include "iodefine.h" #include "lcd_panel.h" #if (LCD_VDC5_CH0_PANEL==1) /****************************************************************************** Macro definitions ******************************************************************************/ /* Port 11 */ #define LCD_PORT11_5TH (0xE0FFu) /* Port 10 */ #define LCD_PORT10_5TH (0xFFFFu) #define FH_1_2_CYCLE (2u) /****************************************************************************** Typedef definitions ******************************************************************************/ /****************************************************************************** Imported global variables and functions (from other files) ******************************************************************************/ /****************************************************************************** Exported global variables (to be accessed by other files) ******************************************************************************/ /****************************************************************************** Private global variables and functions ******************************************************************************/ /**************************************************************************//** * @brief LCD panel I/O port setup (VDC5 channel 0) * @param[in] void * @retval None ******************************************************************************/ void GRAPHICS_SetLcdPanel_Ch0 (void) { // comincia qui start volatile uint16_t dummy_read = 0; volatile uint16_t dummy_read10 = 0; volatile uint16_t dummy_read11 = 0; uint8_t data[0x2]; ///////////////////////////////////////////////////// // PORTA 4 GPIO.PMC4 &= (uint16_t)~0x00FFu; dummy_read = GPIO.PMC4; GPIO.PFCAE4 &= (uint16_t)~0x00FFu; GPIO.PFCE4 &= (uint16_t)~0x00FFu; GPIO.PFC4 &= (uint16_t)~0x00FFu; GPIO.PIPC4 |= (uint16_t)0x00FFu; GPIO.PMC4 |= (uint16_t)0x00FFu; dummy_read11 = GPIO.PMC4; ///////////////////////////////////////////////////// // PORTA 3 GPIO.PMC3 &= (uint16_t)~0xFF00u; dummy_read = GPIO.PMC3; GPIO.PFCAE3 &= (uint16_t)~0xFF00u; GPIO.PFCE3 &= (uint16_t)~0xFF00u; GPIO.PFC3 &= (uint16_t)~0xFF00u; GPIO.PIPC3 |= (uint16_t)0xFF00u; GPIO.PMC3 |= (uint16_t)0xFF00u; dummy_read10 = GPIO.PMC3; // 7 2 1 0 1th alternative function GPIO.PMC3 &= (uint16_t)~0x0087u; dummy_read = GPIO.PMC3; GPIO.PFCAE3 &= (uint16_t)~0x0087u; GPIO.PFCE3 &= (uint16_t)~0x0087u; GPIO.PFC3 &= (uint16_t)~0x0087u; GPIO.PIPC3 |= (uint16_t)0x0087u; GPIO.PMC3 |= (uint16_t)0x0087u; dummy_read10 = GPIO.PMC3; // comincia qui stop } /* End of function GRAPHICS_SetLcdPanel_Ch0() */ static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_VE = { (uint16_t)(LCD_CH0_DISP_VS * 2u), /* Signal pulse start position */ (uint16_t)(LCD_CH0_DISP_VW * 2u), /* Pulse width */ VDC5_LCD_TCON_POLMD_NORMAL, VDC5_LCD_TCON_REFSEL_HSYNC, VDC5_SIG_POL_NOT_INVERTED, /* Polarity inversion control of signal */ VDC5_LCD_TCON_PIN_NON, /* Output pin for LCD driving signal */ LCD_CH0_OUT_EDGE /* Output phase control of signal */ }; /* TCON timing setting, HE */ static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_HE = { (uint16_t)LCD_CH0_DISP_HS, /* Signal pulse start position */ (uint16_t)LCD_CH0_DISP_HW, /* Pulse width */ VDC5_LCD_TCON_POLMD_NORMAL, VDC5_LCD_TCON_REFSEL_HSYNC, /* Signal operating reference select */ VDC5_SIG_POL_NOT_INVERTED, /* Polarity inversion control of signal */ VDC5_LCD_TCON_PIN_NON, /* Output pin for LCD driving signal */ LCD_CH0_OUT_EDGE /* Output phase control of signal */ }; /* TCON timing setting, DE */ static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_DE = { (uint16_t)0, (uint16_t)0, VDC5_LCD_TCON_POLMD_NORMAL, VDC5_LCD_TCON_REFSEL_HSYNC, VDC5_SIG_POL_NOT_INVERTED, /* Polarity inversion control of signal */ VDC5_LCD_TCON_PIN_0, /* Output pin for LCD driving signal */ LCD_CH0_OUT_EDGE /* Output phase control of signal */ }; /**************************************************************************//** * @brief LCD TCON setup parameter acquisition processing (VDC5 channel 0) * @param[out] outctrl : Address of the area for storing the LCD TCON timing setup data table * @retval None ******************************************************************************/ void GRAPHICS_SetLcdTconSettings_Ch0 (const vdc5_lcd_tcon_timing_t * * const outctrl) { /* Analog RGB D-sub15 (RGB888), SVGA signal 800x600 */ /* TCON timing setting, VS */ if (outctrl != NULL) { outctrl[VDC5_LCD_TCONSIG_STVA_VS] = NULL;//&lcd_tcon_timing_VS; /* STVA/VS: Vsync */ outctrl[VDC5_LCD_TCONSIG_STVB_VE] = &lcd_tcon_timing_VE; /* STVB/VE: Not used */ outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = NULL; /* STH/SP/HS: Hsync */ outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = &lcd_tcon_timing_HE; /* STB/LP/HE: Not used */ outctrl[VDC5_LCD_TCONSIG_CPV_GCK] = NULL; /* CPV/GCK: Not used */ outctrl[VDC5_LCD_TCONSIG_POLA] = NULL; /* POLA: Not used */ outctrl[VDC5_LCD_TCONSIG_POLB] = NULL; /* POLB: Not used */ outctrl[VDC5_LCD_TCONSIG_DE] = &lcd_tcon_timing_DE; /* DE: Not used */ } } /* End of function GRAPHICS_SetLcdTconSettings_Ch0() */ #endif /* LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_ANALOG_RGB */ --- end file and lcd_analog_rgb_ch0.h : --- start file /******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /**************************************************************************//** * @file lcd_analog_rgb_ch0.h * @version 0.10 * @brief LCD panel for vdc5 channel 0 definition header ******************************************************************************/ #ifndef LCD_HDMI_RGB_CH0_H #define LCD_HDMI_RGB_CH0_H /****************************************************************************** Includes System Includes , "Project Includes" ******************************************************************************/ #include stdlib.h #include stdio.h #include "r_typedefs.h" #include "r_vdc5.h" //SRSR#define LCD_CH0_DISP_HS (120u) /* LCD display area size, horizontal start position */ #define LCD_CH0_DISP_HS (26u) /* LCD display area size, horizontal start position */ #define LCD_CH0_DISP_HW (800u) /* LCD display area size, horizontal width */ //SRSR#define LCD_DISP_S_HSYNC (868u) //SRSR#define LCD_DISP_W_HSYNC (106u) //SRSR#define LCD_CH0_DISP_VS (29u) /* LCD display area size, vertical start position */ //SRSR#define LCD_CH0_DISP_VW (600u) /* LCD display area size, height (vertical width) */ #define LCD_CH0_DISP_VS (18u) /* LCD display area size, vertical start position */ #define LCD_CH0_DISP_VW (600u) /* LCD display area size, height (vertical width) */ //SRSR#define LCD_DISP_S_VSYNC (0u) //SRSR#define LCD_DISP_W_VSYNC (8u) #define LCD_CH0_SIG_FV (424u - 1u) /* Free-running Vsync period */ #define LCD_CH0_SIG_FH (726u - 1u) /* Hsync period */ //#define LCD_CH0_SIG_FV (210u - 1u) /* Free-running Vsync period */ //#define LCD_CH0_SIG_FH (1000u - 1u) /* Hsync period */ #define LCD_CH0_TCON_HALF (LCD_CH0_SIG_FH / 2u) /* TCON reference timing, 1/2fH timing */ #define LCD_CH0_TCON_OFFSET (0u) /* TCON reference timing, offset Hsync signal timing */ #define LCD_CH0_PANEL_CLK VDC5_PANEL_ICKSEL_PERI /* Panel clock select */ #define LCD_CH0_PANEL_CLK_DIV VDC5_PANEL_CLKDIV_1_2 /* Panel clock frequency division ratio */ #define LCD_CH0_OUT_EDGE VDC5_EDGE_RISING /* Output phase control of LCD_DATA[23:0] signal */ #define LCD_CH0_OUT_FORMAT VDC5_LCD_OUTFORMAT_RGB565 /* LCD output format select */ /****************************************************************************** Typedef definitions ******************************************************************************/ /****************************************************************************** Exported global functions (to be accessed by other files) ******************************************************************************/ void Graphics_SetLcdPanel_Ch0(void); void Graphics_SetLcdTconSettings_Ch0(const vdc5_lcd_tcon_timing_t * * outctrl); #endif /* LCD_HDMI_RGB_CH0_H */ --- end file This is the linker script file kpitgcc.ld I used: --- start file MEMORY { ROM (rx) : ORIGIN = 0x00000000, LENGTH = 128M SYSTEM_RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x04000 STACK (rw) : ORIGIN = 0x20024000, LENGTH = 0x14000 CACHED_RAM (rx) : ORIGIN = 0x20039000, LENGTH = 0x000A7000 /* For RAM_only */ READ_ONLY_RAM (rw) : ORIGIN = 0x600E0000, LENGTH = 0x00320000 /* For RAM_only */ UNCACHED_RAM (rw) : ORIGIN = 0x60400000, LENGTH = 0x00600000 SDRAM2 (rw) : ORIGIN = 0x08000000, LENGTH = 0x04000000 SDRAM1 (rw) : ORIGIN = 0x0C000000, LENGTH = 0x04000000 } SECTIONS { .text : { . = 0x00000000; * (VECTOR_TABLE) /*asm*/ . = 0x00000200; * (RESET_HANDLER) /*asm*/ * (INIT_TTB) /*asm*/ * (INITCA9CACHE) /*asm*/ * (CODE_BASIC_SETUP) */peripheral_init_basic.o (.text .text.*) */bsc.o (.text .text.*) */bsc_userdef.o (.text .text.*) * (CONST_BASIC_SETUP) */peripheral_init_basic.o (.rodata .rodata.*) */bsc.o (.rodata .rodata.*) */bsc_userdef.o (.rodata .rodata.*) * (CODE_IRQ_HANDLER) /*asm*/ * (InRoot$$Sections) * (CODE_FPU_INIT) /*nothing*/ * (FPU_INIT) /*asm*/ * (CONST_FPU_INIT) /*nothing*/ * (CODE_RESET) /*asm*/ */port_init.o (.text .text.*) */stb_init.o (.text .text.*) */cache.o (.text .text.*) */resetprg.o (.text .text.*) * (INIT_VBAR) /*asm*/ * (CONST_RESET) /*asm*/ */sections.o (.rodata .rodata.*) */port_init.o (.rodata .rodata.*) */stb_init.o (.rodata .rodata.*) */cache.o (.rodata .rodata.*) */resetprg.o (.rodata .rodata.*) * (CODE_IO_REGRW) */rza_io_regrw.o (.text .text.*) * (CONST_IO_REGRW) */rza_io_regrw.o (.rodata .rodata.*) } READ_ONLY_RAM /* For RAM_only */ /* The vector mirror table and the irq handler must include in the .data section. Because the addresses on ROM are not calculated if the two put in each sections. */ .data : { . = 0x00000000; __vect_load = .; __vect_start = LOADADDR(.data) + ( __vect_load - ADDR(.data) ); Image$$VECTOR_MIRROR_TABLE$$Base = .; * (VECTOR_MIRROR_TABLE) /*asm*/ __vect_end = LOADADDR(.data) + ( . - ADDR(.data) ); /********************************************************************/ . = 0x00000100; __fastcode_load = .; __fastcode_start = LOADADDR(.data) + ( __fastcode_load - ADDR(.data) ); * (CODE_HANDLER_JMPTBL) */intc_userdef.o (.text .text.*) * (CONST_HANDLER_JMPTBL) */intc_userdef.o (.rodata .rodata.*) * (IRQ_FIQ_HANDLER) /*asm*/ * (CODE_HANDLER) */intc_handler.o (.text .text.*) * (CONST_HANDLER) */intc_handler.o (.rodata .rodata.*) __fastcode_end = LOADADDR(.data) + ( . - ADDR(.data) ); /********************************************************************/ __data_load = .; __data_start = LOADADDR(.data) + ( __data_load - ADDR(.data) ); * (DATA_HANDLER_JMPTBL) */intc_userdef.o (.data) * (DATA_BASIC_SETUP) */peripheral_init_basic.o (.data) */bsc.o (.data) */bsc_userdef.o (.data) * (DATA_HANDLER) */intc_handler.o (.data) * (DATA_FPU_INIT) /*nothing*/ * (DATA_RESET) */port_init.o (.data) */stb_init.o (.data) */cache.c (.data) */resetprg.c (.data) * (DATA_IO_REGRW) */rza_io_regrw.o (.data) * (.data .data.*) __data_end = LOADADDR(.data) + ( . - ADDR(.data) ); PROVIDE_HIDDEN(__exidx_start = .); PROVIDE_HIDDEN(__exidx_end = .); } SYSTEM_RAM AT READ_ONLY_RAM /* For RAM_only */ .bss : { __bss_start = .; * (BSS_HANDLER_JMPTBL) */intc_userdef.o (.bss) * (BSS_BASIC_SETUP) */peripheral_init_basic.o (.bss) */bsc.o (.bss) */bsc_userdef.o (.bss) * (BSS_HANDLER) */intc_handler.o (.bss) * (BSS_FPU_INIT) /*nothing*/ * (BSS_RESET) */port_init.o (.bss) */stb_init.o (.bss) */cache.c (.bss) */resetprg.c (.bss) * (BSS_IO_REGRW) */rza_io_regrw.o (.bss) __bss_end = .; } CACHED_RAM .stack : { . = ALIGN( 0x10 ); Image$$ARM_LIB_STACK$$ZI$$Base = .; . += 0x00008000; Image$$ARM_LIB_STACK$$ZI$$Limit = .; . = ALIGN( 0x10 ); Image$$IRQ_STACK$$ZI$$Base = .; . += 0x00002000; Image$$IRQ_STACK$$ZI$$Limit = .; . = ALIGN( 0x10 ); Image$$FIQ_STACK$$ZI$$Base = .; . += 0x00002000; Image$$FIQ_STACK$$ZI$$Limit = .; . = ALIGN( 0x10 ); Image$$SVC_STACK$$ZI$$Base = .; . += 0x00002000; Image$$SVC_STACK$$ZI$$Limit = .; . = ALIGN( 0x10 ); Image$$ABT_STACK$$ZI$$Base = .; . += 0x00002000; Image$$ABT_STACK$$ZI$$Limit = .; . = ALIGN( 0x4000 ); Image$$TTB$$ZI$$Base = .; . += 0x00004000; Image$$TTB$$ZI$$Limit = .; } STACK .uncached_RAM (NOLOAD) : { * (VRAM) * (.WORK_SECTION1) * (.WORK_SECTION2) } UNCACHED_RAM .text2 : { * (.text .text.*) * (.rodata .rodata.*) } READ_ONLY_RAM /* For RAM_only */ .data2 : { __data2_load = .; __data2_start = LOADADDR(.data2) + ( __data2_load - ADDR(.data2) ); * (.data .data.*) __data2_end = LOADADDR(.data2) + ( . - ADDR(.data2) ); } CACHED_RAM AT READ_ONLY_RAM /* For RAM_only */ .bss2 : { __bss2_start = .; * (.bss .bss.*) * (COMMON) __bss2_end = .; . = ALIGN( 0x4 ); /* Because heap memory manager refers "end" at next line */ end = .; __heap_start = .; * (HEAP) . = . + 0x00040000; __heap_end = .; . = . + 0x00040000; stack_ptr = .; } CACHED_RAM .SDRAM2 (NOLOAD) : { __SDRAM2_start = .; * (VRAM_EX) * (SDRAM_NS) __SDRAM2_end = .; } SDRAM2 .dummy : { . = 0x0100; } ROM = 0x00 } --- end file
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