Hi guys! Good day! Sorry I didn't write any feedback after the last comments... Well, I did take in consideration the comment, but, for me, the issue is not closed...See below my considerations: - Figure in question (8-55) is not clear that this also applies to the mode 8.5.4 Reset Synchronous PWM Mode, as this figure is part of the previous section 8.5.3 PWM Function; - Even if the figure 8-55 apply to reset sync mode, it is not clear the functional relationship between buffer register and the main duty cycle register (i.e TRDGRD0 - TRDGRB0) on the issue of updating the DC. For example, when it said: "When compare matches with registers TRDGRAi and TRDGRBi are generated simultaneously, the compare match with the TRDGRBi register has priority. A low level is applied to the TRDIOBi output without any change.", but in this case, the priority can be applied for all the time, not just for one cycle.... In the case, it would be clear only if we had available figures as "Figure 8-66" and "Figure 8-67", which are complementary mode... I am also in contact with Renesas support to clarify this matter, but they are evaluating and analyzing it yet...However, the behavior seems to happen as expected, but it is not clear with the datasheet graphs... As soon I got some closure, I will post here.... Thanks for your attention!
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