Dirk, It's not clear from your code where the SCR TE and RE are set to 1 to enable transmission. If you review the SCIe timing diagram shown in the H/W manual for your particular processor you will see there is a finite amount of time when the 1st byte is written to the buffer to when the transmission starts. It might also be worth reviewing the flowcharts in that section as well. It's possible that the processor is buffering the 1st byte of data into the transmit buffer and not sending it because of the enable bit set as well. twelvexs
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