Thanks for the extra info. Does anyone know what the actual cache block size for an RZ is? I want to make sure I don't read from the same cache block while DMA is taking place. The manual says 32 Kbytes L1 data cache, and it says 128 TLB entries, but it's not clear whether that's 128 for the data cache, or for the data and instruction caches combined. So it sounds like either 256 bytes or 512 bytes per cache block? Also, would there be an easy way to switch caching off outside of a given memory region, e.g. below 0x2000_0000 ? Or, I've got a hunch that using the "mirror areas" in the address space might bypass caching, could that be correct?
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