Hello Kirin, Thanks for your time. Could you please tell me where you found the info regarding the output impedance? I could not find it in the hw manual nor the datasheet. All I could find is that the output HIGH voltage is VCC-0.5V @ 1mA load. This means that the output PMOS transistor has a 0.5V voltage drop at this load. Wouldn't the equivalent resistance then be: 500 Ohm ? Also, the current through the capacitor is determined by i=C*(dv/dt) and the output impedance "i.e. series resistor". So, in order to simulate that the current does not exceed 4 mA, I would need to know the rise/fall time to evaluate dv/dt. Then I could simulate it in LTSpice. Is this the way to accurately figure whether an external series resistor is needed for a certain size of load capacitor in order not to exceed the 4mA maximum I/O rating? Or are transient effects treated differently? Regards, HC
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